1. Field of the Invention
The present invention relates to a metal interconnection structure of a semiconductor device and a method of forming the same.
2. Description of the Related Art
As semiconductor devices become more highly integrated, metal lines become increasingly multi-layered. Therefore, metal interconnection structures and the methods of forming the metal interconnection structures have been actively researched and developed in order to improve performance of the semiconductor devices.
FIG. 1 is a cross sectional view for explaining an example of a conventional method of manufacturing a metal interconnection structure.
Referring to FIG. 1, an interlayer insulating layer 102 is formed on a semiconductor substrate 101. Next, a contact hole 103 is formed to penetrate the interlayer insulating layer 102 and expose an active region of the semiconductor substrate 101. Next, a metal contact 104 is formed to fill the contact hole 103 with a metal layer. Next, an insulating layer 105 is formed on the interlayer insulating layer 102 and the contact hole 103. Next, a trench is formed to penetrate the insulating layer 105 and expose an upper surface of the metal contact 104. Next, a lower metal layer 106 is formed to fill the trench with a metal layer. Next, an inter-metal dielectric layer 107, a via hole 108, a via contact 109, and an upper metal layer 110 are formed with the same as the aforementioned steps.
On the other hand, as copper (Cu) lines having excellent electrical characteristics become more popular, techniques for forming metal interconnection structures by using a damascene method have been widely used.
FIG. 2 is a cross sectional view showing a metal interconnection structure formed by using the damascene method.
Referring to FIG. 2, an insulating layer 202 is formed on an underlying layer 201. Next, a trench 203 is formed by removing a portion of an upper portion of the insulating layer 202. Next, a contact hole 204 having a narrower width than the trench 203 is formed to penetrate the insulating layer 202 from the bottom surface of the trench 205. Next, an insulating layer 206 is formed on the insulating layer 202 and the metal layer 205. Next, the trench 203 and the contact hole 204 are filled with a lower metal layer 205, and then, a planarization process is performed. Subsequently, a trench 207 is formed by removing a portion of an upper portion of the insulating layer 206. Next, a contact hole 208 having a narrow width than the trench 207 is formed to penetrate the insulating layer 206 from the bottom surface of the trench 207. Next, the trench 207 and the contact hole 208 are filled with an upper metal layer 209, and then, a planarization process is performed.
By using the damascene method, Cu metal lines having excellent electrical characteristics can be easily implemented. On the other hand, in order to improve characteristics of the semiconductor devices, techniques of using an insulating layer having a low dielectric constant to insulate the lower metal layer 205 from the upper metal layer 209 have been researched and developed.
Currently, an insulating layer having a dielectric constant of about 2.0 to 3.0 has been researched. However, in a metal interconnection structure using the insulating layer having a low dielectric constant and a method of forming the metal interconnection structure, there are various problems. Therefore, it is expected that it takes a relatively long time to implement a practical metal interconnection structure using the insulating layer having a low dielectric constant.